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mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 1 2006/4 ver1.1 1. general description this eprom-based 8-bit micro-controller uses a fully static cmos design technology combines higher speeds and smaller size with the low power and high noise immunity. on chip memory system includes 1.0 k words of rom, and 32 bytes of static ram. 2. features the followings are some of the features on the hardware and software : fully cmos static design 8-bit data bus on chip rom size : 1k words internal ram size : 32 bytes (25 general purpose registers, 7 special registers) 36 single word instructions 14-bit instructions 2-level stacks operating voltage : 2.3v ~ 6.0 v operating frequency : 0 ~ 20 mhz the most fast execution time is 200 ns under 20 mhz in all single cycle instructions except the branch instructions addressing modes include direct, indirect and relative addressing modes power-on reset (por) only available while ped is disable power edge-detector reset (ped) sleep mode for power saving 8-bit real time clock/counter(rtcc) with 8-bit programmable prescaler 4 types of oscillator can be selected by programming option (internal capacitor about 10p ): rc ? low cost rc oscillator lfxt ? low frequency crystal oscillator xtal ? standard crystal oscillator hfxt ? high frequency crystal oscillator 4 oscillator start-up time can be selected by programming option: 150 s, 20 ms, 40 ms, 80 ms on-chip rc oscillator based watchdog timer(wdt) can be operated freely 12 i/o pins with their own independent direction control 3. applications the application areas of this mdt10p10 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as remote controller, small instruments, chargers, toy, automobile and pc peripheral ? etc.
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 2 2006/4 ver1.1 4. pin assignment dip / sop pa2 1 18 pa1 pa3 2 17 pa0 rtcc 3 16 osc1 /mclr 4 15 osc2 v ss 5 14 v dd pb0 6 13 pb7 pb1 7 12 pb6 pb2 8 11 pb5 pb3 9 10 pb4 ssop pa2 1 20 pa1 pa3 2 19 pa0 rtcc 3 18 osc1 /mclr 4 17 osc2 vss 5 16 vdd vss 6 15 vdd pb0 7 14 pb7 pb1 8 13 pb6 pb2 9 12 pb5 pb3 10 11 pb4 5. pin function description pin name i/o function description pa0~pa3 i/o port a, ttl input level pb0~pb7 i/o port b, ttl input level rtcc i real time clock/counter, schmitt trigger input levels /mclr i master clear, schmitt trigger input levels osc1 i oscillator input osc2 o oscillator output v dd power supply v ss ground 6. memory map (a) register map address description 00 indirect addressing register 01 rtcc 02 pc 03 status
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 3 2006/4 ver1.1 address description 04 msr 05 port a 06 port b 07~1f internal ram, general purpose register (1) iar ( indirect address register) : r0 (2) rtcc (real time counter/counter register) : r1 (3) pc (program counter) : r2 write pc, call --- always 0 ljump, jump, lcall --- from instruction word rtwi, ret --- from stack a9 a8 a7~a0 write pc, jump, call --- always 0 (rom 1.0k) ljump, lcall --- from instruction word rtwi, ret --- from stack write pc --- from alu ljump, jump, lcall, call --- from instruction word rtwi, ret --- from stack (4) status (status register) : r3 bit symbol function 0 1 2 3 4 5 6 { 7 c hc z pf tf page 0 {{ carry bit half carry bit zero bit power loss flag bit time overflow flag bit page select bit : 0 : 000h --- 1ffh 1 : 200h --- 3ffh general purpose bit
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 4 2006/4 ver1.1 (5) msr (memory select register) : r4 (6) port a : r5 pa3~pa0, i/o register (7) port b : r6 pb7~pb0, i/o register (8) tmr (time mode register) bit symbol function prescaler value rtcc rate wdt rate 2 { 0 ps2 { 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 3 psc prescaler assignment bit : 0 { rtcc 1 { watchdog timer 4 tce rtcc signal edge : 0 { increment on low-to-high transition on rtcc pin 1 { increment on high-to-low transition on rtcc pin 5 tcs rtcc signal set : 0 { internal instruction cycle clock 1 { transition on rtcc pin (9) cpio a, cpio b (control port i/o mode register) the cpio register is ?write-only? ? ?0?, i/o pin in output mode; ? ?1?, i/o pin in input mode. (10) eprom option by writer programming : oscillator type oscillator start-up time rc oscillator 150 s,20ms,40ms,80ms hfxt oscillator 20 ms,40ms,80ms xtal oscillator 20ms,40 ms,80ms lfxt oscillator 40 ms,80 ms
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 5 2006/4 ver1.1 watchdog timer control watchdog timer disable all the time watchdog timer enable all the time power edge detect security bit ped disable security disable ped enable security enable the default eprom security is disable. once t he ic was set to enable, it can not set to disable again. (b) program memory address description 000-3ff program memory for mdt10p10 3ff the starting address of the power on, external reset or wdt time-out reset for mdt10p10 7. reset condition for all registers register address power-on reset /mclr or wdt reset cpio a ?? 1111 1111 1111 1111 cpio b ?? 1111 1111 1111 1111 tmr ?? - - 11 1111 - - 11 1111 iar 00h xxxx xxxx uuuu uuuu rtcc 01h xxxx xxxx uuuu uuuu pc 02h 1111 1111 1111 1111 status 03h 0001 1 xxx 000# #uuu msr 04h 111x xxxx 111u uuuu port a 05h - - - - xxxx - - - - uuuu port b 06h xxxx xxxx uuuu uuuu note : u ? unchanged, x ? unknown, - ? unimplemented, read as ?0? # ? value depends on the condition of the following table
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 6 2006/4 ver1.1 condition status: bit 4 status: bit 3 /mclr reset (not during sleep) u u /mclr reset during sleep 1 0 wdt reset (not during sleep) 0 1 wdt reset during sleep 0 0 8. instruction set instruction code mnemonic operands function operating status 010000 00000000 nop no operation none 010000 00000001 clrwt clear watchdog timer 0 wt tf, pf 010000 00000010 sleep sleep mode 0 wt, stop osc tf, pf 010000 00000011 tmode load w to tmode register w tmode none 010000 00000100 ret return stack pc none 010000 00000rrr cpio r cont rol i/o port register w cpio r none 010001 1 rrrrrrr stwr r store w to register w r none 011000 t rrrrrrr ldr r, t load register r t z 111010 iiiiiiii ldwi i load immediate to w i w none 010111 t rrrrrrr swapr r, t sw ap halves register [r(0~3) ? r(4~7)] t none 011001 t rrrrrrr i ncr r, t increment register r + 1 t z 011010 t rrrrrrr i ncrsz r, t increment register, skip if zero r + 1 t none 011011 t rrrrrrr addwr r, t add w and register w + r t c, hc, z 011100 t rrrrrrr subwr r, t subtract w from register r w t (r+/w+1 t) c, hc, z 011101 t rrrrrrr decr r, t decrement register r 1 t z 011110 t rrrrrrr decrsz r, t decrement register, skip if zero r 1 t none 010010 t rrrrrrr andwr r, t and w and register r ? w t z 110100 iiiiiiii andwi i and w and immediate i ? w w z 010011 t rrrrrrr iorwr r, t inclu. or w and register r ? w t z 110101 iiiiiiii iorwi i inclu. or w and immediate i ? w w z 010100 t rrrrrrr xorwr r, t exclu. or w and register r w t z 110110 iiiiiiii xorwi i exclu. or w and immediate i w w z 011111 t rrrrrrr comr r, t complement register /r t z 010110 t rrrrrrr rrr r, t rotate right register r(n) r(n-1), c r(7), r(0) c c
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 7 2006/4 ver1.1 instruction code mnemonic operands function operating status 010101 t rrrrrrr rlr r, t rotate left register r(n) r(n+1),c r(0), r(7) c c 010000 1 xxxxxxx clrw clear working register 0 w z 010001 0 rrrrrrr clrr r clear register 0 r z 0000bb b rrrrrrr bcr r, b bit clear 0 r(b) none 0010bb b rrrrrrr bsr r, b bit set 1 r(b) none 0001bb b rrrrrrr btsc r, b bit test, skip if clear skip if r(b)=0 none 0011bb b rrrrrrr btss r, b bit test, skip if set skip if r(b)=1 none 1000nn nnnnnnnn lcall n long call subroutine n pc, pc+1 stack none 1010nn nnnnnnnn ljump n long jump to address n pc none 110000 nnnnnnnn call n call subroutine n pc, pc+1 stack none 110001 iiiiiiii rtwi i return, place immediate to w stack pc, i w none 11001n nnnnnnnn jump n jump to address n pc none note : w : working register b : bit position wt : watchdog timer t : target tmode : tmode mode register 0 : working register cpio : control i/o port register 1 : general register tf : timer overflow flag r : general register address pf : power loss flag c : carry flag pc : program counter hc : half carry osc : oscillator z : zero flag inclu. : inclusive ? ? ? / : complement exclu. : exclusive ? ? x : don?t care and : logic and ? ? ? i : immediate data ( 8 bits ) n : immediate address 9. electrical characteristics (a) operating voltage & frequency v dd u 2.3v ~ 6.0 v frequency u 0 hz ~ 20 mhz
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 8 2006/4 ver1.1 (b) input voltage @ v dd ? 5.0 v, temperature ? 25
port min. max. v il pa, pb rtcc, /mclr v ss v ss 1.0 v 1.0v v ih pa, pb rtcc, /mclr 2.0 v 3.1 v v dd v dd threshold voltage : port a, port b v th ? 1.5v rtcc/mclr v v il ? 1.2v, v ih ? 3.0v (schmitt trigger) (c) output voltage u @ v dd ? 5.0 v, temperature ? 25
, the typical value as followings : pa, pb port i oh ?? 20.0 ma v oh ? 3.6 v i ol ? 20.0 ma v ol ? 0.6 v i oh ?? 5.0 ma v oh ? 4.6 v i ol ? 5.0 ma v ol ? 0.3 v (d) leakage current @ v dd ? 5.0 v, temperature ? 25
, the typical value as followings : i il ? 0.1 a (max.) i ih e 0.1 a (max.) (e) sleep current @wdt ? disable, ped-disable temperature ? 25
, the typical value as followings : v dd ? 2.3 v i dd ? 0.1 a v dd ? 3.0 v i dd ? 0.1 a v dd ? 4.0 v i dd ? 0.1 a v dd ? 5.0 v i dd ? 0.1 a v dd ? 6.0v i dd ? 0.1 a
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 9 2006/4 ver1.1 @wdt ? enable , ped-disable temperature ? 25
, the typical value as followings : v dd ? 2.3 v i dd ? 1.0 a v dd ? 3.0 v i dd ? 3.0 a v dd ? 4.0 v i dd ? 7.5 a v dd ? 5.0 v i dd ? 16.0 a v dd ? 6.0 v i dd ? 26.0 a (f) typical operating current : ( temperature ? 25
) (i) osc type ? rc (osc1&osc2 internal cap about 10p); wdt ? enable; the ic may not oscillate properly if the resistance of rext less than 4.7k. the minimum resistance of rext must be more than 4.7k. @ v dd ? 5.0 v cext. (f) rext. (ohm) frequency (hz) current (a) 4.7 k 11.5 m 1.2 ma 10.0 k 5.3 m 700 a 0p 47.0 k 1.3 m 250 a 100.0 k 628 k 200 a 300.0 k 215 k 140 a 470.0 k 135 k 135 a 4.7 k 9.3 m 1.1 ma 10.0 k 4.4 m 540 a 3p 47.0 k 1.05 m 225 a 100.0 k 540 k 160 a 300.0 k 170 k 130 a 470.0 k 110 k 120 a 4.7 k 5.4 m 630 a 10.0 k 2.4 m 340 a 20p 47.0 k 600 k 170 a 100.0 k 285 k 140 a 300.0 k 110 k 120 a 470.0 k 55 k 110 a
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 10 2006/4 ver1.1 cext. (f) rext. (ohm) frequency (hz) current (a) 4.7 k 2.0 m 310 a 10.0 k 1.0 m 220 a 100p 47.0 k 230 k 140 a 100.0 k 110 k 130 a 300.0 k 35 k 110 a 470.0 k 20 k 100 a 4.7 k 900 k 200 a 10.0 k 400 k 180 a 300p 47.0 k 90 k 115 a 100.0 k 40 k 110 a 300.0 k 14 k 105 a 470.0 k 9.2 k 100 a (ii) osc type ? lf (osc1 &osc2 internal cap); wdt ? disable t ped=enable voltage/frequency 32 k (ext c=50p) 455 k (ext c=50p) 1 m sleep 2.3 v 11 a 22 a @2.4v 35 a ? 0.1 a 3.0 v 19 a 40 a 50 a ? 0.1 a 4.0 v 40 a 75 a 85 a ? 0.1 a 5.0 v 70 a 120 a 140 a ? 0.1 a 6.0 v 125 a 200 a 220 a ? 0.1 a (iii) osc type ? xt(osc1&osc2 internal cap about 10p); wdt ? enable voltage/frequency 1 m 4 m 10 m sleep 2.3 v 32 a 100 a 230 a ? 1.0 a 3.0 v 75 a 180 a 385 a 3.0 a 4.0 v 155 a 300 a 610 a 7.5 a 5.0 v 250 a 440 a 950 a 16 a 6.0 v 400 a 650 a 1.2 ma 27 a
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 11 2006/4 ver1.1 (iv) osc type ? hf (osc1& osc2 internal cap about 10p) t wdt ? enable voltage/frequency 4 m 10 m 20 m sleep 2.3 v 100 a 230 a @2.5v 590 a ? 1.0 a 3.0 v 200 a 420 a 750 a 3.0 a 4.0 v 340 a 650 a 1.1 ma 7.5 a 5.0 v 540 a 900 a 1.7 ma 16 a 6.0 v 900 a 1.25 ma 2.35 ma 27 a (g)the basic wdt time-out cycle time @ v dd= 5.0v ,temperature ? 25
, the typical value as followings : voltage (v) basic wdt time-out cycle time (ms) 2.3 23.5 3.0 21.5 4.0 20.3 5.0 18.3 6.0 17.5
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 12 2006/4 ver1.1 (h) reset & watchdog timer timing vdd /mclr internal por ost time-out internal reset wdt reset i/o pin tost watchdog timer time-out period oscillator start up time twdt tio i/o floating from /mclr low tmclr /mclr pulse width 15 20 24 100 500 15 20 24 ms ms ns ns min typ max unit description symbol tost tost tio tio tmclr twdt (no postscaler) /mclr, watchdog timer and internal por timing (i) power edge-detector reset voltage (not in sleep mode), @ v dd ? 5.0 v(ped j enable) v pr 1.6~1.9 v v pr u v dd (power supply) ps.if ped_enable then internal power_on_reset will be off
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 13 2006/4 ver1.1 (j) mclrb filter j @ v dd= 5.0v wm 1.2us wm : filter pulse width (low) in /mclr pin. 10. port a and port b equivalent circuit working register i/o control write data bus read data o/p latch d ck d i/o control latch ck q b q q ck q b d input resistor port i/o pin data i/p latch ttl input level data i/p
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 14 2006/4 ver1.1 11. mclrb and rtcc input equivalent circuit 3y, 4dinjuu5sjhhfs .$-3# r y 1 k schmitt trigger rtcc
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 15 2006/4 ver1.1 12. block diagram 4ubdl5xp-fwfmt 1sphsbn$pvoufst 0tdjmmbups$jsdvju 1pxfspo3ftfu 1pxfs%pxo3ftfu cju5jnfs$pvoufs &130. .%51
*otusvdujpo 3fhjtufs *otusvdujpo %fdpefs 8psljoh3fhjtufs "-6 1sftdbmf 3". 4qfdjbm3fhjtufs $pouspm$jsdvju 4ubuvt3fhjtufs 8%5045 5jnfs 1psu" 1psu# 04$ 04$ .$-3 data 8-bit rtcc 9 or10 bits 9 or 10 bits 14 bits 1psu 1"_1" cjut 1psu 1#_1# cjut d0~d7
mdt10p10(bg) this specification are subject to be changed without notice. any latest information please preview ttp;//www.mdtic.com.tw p. 16 2006/4 ver1.1 13. internal capacitor selection for crystal oscillator @ v dd ? 3.0v~5.0 v osc. type resonator freq. c1 c2 20 mhz 0 pf ~10 pf 0 pf ~20 pf hf 10 mhz 0 pf ~50 pf 0 pf ~100 pf 4 mhz 0 pf ~30 pf 0 pf ~100 pf 10 mhz 0 pf ~30 pf 0 pf ~50 pf xt 4 mhz 0 pf ~50 pf 0 pf ~100 pf 1 mhz 0 pf ~30 pf 0 pf ~50 pf 1 mhz 5 pf ~10 pf 5 pf ~10 pf lf 455 k 10 pf ~50 pf 10 pf ~50 pf 32 k 10 pf ~30 pf 20 pf ~50 pf to increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range can be recommended for reference, but the higher capacitance also increases the start-up time.

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